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About the frontpanel category
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0
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1782
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May 11, 2014
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okRegisterBridge : How to Assert regRead for Multiple Consecutive Cycles? (XEM7310)
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0
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4
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January 2, 2025
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About Host simulation; reinvoke(relaunch) & Xilinx IP simulation
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0
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8
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November 27, 2024
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Operation of "IsTriggered" function in HDL simulations
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4
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21
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November 23, 2024
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Front Panel HDL synthesis on Windows 11 fails
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3
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19
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November 8, 2024
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Automating okFilePipe method (FPGA to PC)
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1
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23
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October 10, 2024
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XEM7310 bank 35 voltage issue
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0
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23
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August 6, 2024
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Vivado sim error, XEM7360 okCoreHarness : error generated
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2
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744
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July 23, 2024
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Failed to claim USB interface: Device or resource busy (error 16) under Ubuntu
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0
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102
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July 10, 2024
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Port width mismatch for port 'ep_datain' in okWireOut
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7
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90
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June 26, 2024
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Multiple XEM 7310 boards on Ubuntu 20 LTS
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0
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110
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June 4, 2024
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[C++] Incorrect number of devices shown
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3
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1903
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May 28, 2024
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Different okHost Ports for Simulation vs. Implementation XEM8350
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2
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656
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May 24, 2024
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okClk not toggling on xem7320
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0
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109
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May 15, 2024
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Recommended method to Transfer data from PC to FPGA - USB3.0
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2
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331
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April 23, 2024
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Need sample program for okFilePipe
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0
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206
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January 30, 2024
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FrontPanel 5.3.0 and Fedora Linux
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3
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281
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December 24, 2023
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Limited datarate for high speed data from sensor
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0
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214
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December 19, 2023
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Upgrade from 5.0.2 to 5.2.12
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0
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252
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December 1, 2023
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Unable to use the FrontPanel Python API
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1
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447
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October 21, 2023
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Synthesizing the DES code
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1
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314
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September 22, 2023
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okClks frequency - XEM8350
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3
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336
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September 22, 2023
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Front Panel / MATLAB interface missing functions
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0
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460
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September 14, 2023
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How I can download my bitflie into the flash, so that I don't need download into FPGA every time when it power on?
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1
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358
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August 25, 2023
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Is there a clksrc_div3byn for okCPLL22150?
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0
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265
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August 8, 2023
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FrontPanel Unsatisfied link error MacOS
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1
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447
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August 3, 2023
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Access via Docker
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3
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823
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August 3, 2023
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Using SZG-DAC-AD9116
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1
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401
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June 14, 2023
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DES Example For LabVIEW
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14
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591
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June 12, 2023
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XEM7320 with SYZYGY ADC
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1
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441
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June 9, 2023
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